m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 380

• Manufacturer Part Number: m30833fjgp
• Description: Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
• Manufacturer: Renesas Electronics Corporation.

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22.3 CAN Interrupts
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3
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Figure 22.30 Operation Timing when CAN Bus Error Occurs
2
0
22.2.4 CAN Bus Error Timing
The CANj interrupt (j=0 to 2) is provided as the CAN interrupt. Figure 22.31 shows a block diagram of the
CAN interrupt.
The following factors cause the CAN-associated interrupt request to be generated.
C
1
9
3 .
B
8 /
Figure 22.30 shows an operation example of when a CAN bus error occurs.
The CANj interrupt, caused by one of the CANi interrupt request factors listed above, is generated via
the OR circuit.
If an interrupt request factor is established, the corresponding bit in the C0SISTR register is set to "1"
(interrupt requested) when the CAN0 slot k completes a transmission or a reception. The corresponding
bit in the C0EISTR register is set to "1" (interrupt requested) when the CANi module detects a bus error,
moves into an error-passive state, or moves into a bus-off state.
The CAN0 interrupt request signal is set to "1" when the corresponding bit in the C0SISTR or C0EISTR
is set to "1" and the corresponding bit in the C0SIMKR or C0EIMKR is set to "1".
When the CAN0 interrupt request signal changes from "0" to "1", all CANjR bits in the IIO9IR to IIO11IR
registers are set to "1" (interrupt requested).
If at least one of the CANjE bits in the IIO9IE to IIO11IE registers is set to "1" (interrupt enabled), the IR
bits in the corresponding CANjIC registers are set to "1" (interrupt requested). The CAN0 interrupt
request signal remains set to "1" if another interrupt request causes a corresponding bit in the C0SISTR
or C0EISTR to be set to "1" and the corresponding bit in the C0SIMKR or C0EIMKR to be set to "1" after
the CAN0 interrupt request signal changes "0" to "1". The CANjR and IR bits also remain unchanged.
Bits in the C0SISTR or C0EISTR register and CANjR bits (j=0 to 2) in the IIO9IR to IIO11IR registers are
not set to "0" automatically, interrupt acknowledgment notwithstanding. Set these bits to "0" by pro-
gram.
The CANi interrupts are acknowledged when the CANjR bit in the IIO9IR to IIO11IR register and the
corresponding bit in the C0SISTR or C0EISTR register, which are set to enable interrupts though setting
the C0SIMKR or C0EIMKR register, are set to "0". If these bits remain set to "1", all CAN-associated
interrupt request factors become invalid.
- The CAN0 slot i (i=0 to 15) completes a transmission
- The CAN0 slot i completes a reception
- The CAN0 module detects a bus error
- The CAN0 module moves into an error-passive state
- The CAN0 module moves into a bus-off state
0
1
3
0
(1) When a CAN bus error is detected, the STATE_BUSERROR bit in the CiSTR register is set to "1",
3
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G
4
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0 -
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(error occurred) and the BEIS bit in the CiEISTR register is set to "1" (interrupt requested). The
CAN starts transmitting the error frame.
3 .
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, 1
3
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1
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2
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0
0
3
6
2
C
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Page 357
CAN bus
STATE_BUSERROR
bit
BEIS bit
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3
2
C
f o
8 /
4
3
8
) T
8
"1"
"0"
"1"
"0"
Transmit / receive frame
(1)
Error detected
Error frame
22. CAN Module