psd835g2 STMicroelectronics, psd835g2 Datasheet - Page 94

• Manufacturer Part Number: psd835g2
• Description: Configurable Memory System On A Chip For 8-bit Microcontrollers
• Manufacturer: STMicroelectronics

Reset timing and device status at Reset
Table 26.
1. The SR_cod and PeriphMode bits in the VM register are always cleared to ’0’ on Power-Up Reset or Warm Reset.
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MCU I/O
PLD Output
Address Out
Data port
Peripheral I/O
PMMR0 and PMMR2
Macrocells flip-flop status
VM register
All other registers
Port Configuration
Register
(1)
Status during Power-Up Reset, Warm Reset and Power-down mode
Input mode
Valid after internal PSD
configuration bits are
loaded
Tri-stated
Tri-stated
Tri-stated
Cleared to ’0’
Cleared to ’0’ by internal
Power-Up Reset
Initialized, based on the
selection in PSDsoft
Configuration menu
Cleared to ’0’
Power-Up Reset
Power-Un Reset
Input mode
Valid
Tri-stated
Tri-stated
Tri-stated
Unchanged
Depends on .re and .pr
equations
Initialized, based on the
selection in PSDsoft
Configuration menu
Cleared to ’0’
Warm Reset
Warm Reset
Unchanged
Depends on inputs to PLD
(addresses are blocked in
PD mode)
Not defined
Tri-stated
Tri-stated
Unchanged
Depends on .re and .pr
equations
Unchanged
Unchanged
Power-down mode
Power-down mode
PSD835G2