psd835g2 STMicroelectronics, psd835g2 Datasheet - Page 113

• Manufacturer Part Number: psd835g2
• Description: Configurable Memory System On A Chip For 8-bit Microcontrollers
• Manufacturer: STMicroelectronics

PSD835G2
Table 46.
1. t
Figure 47. Reset (RESET) timing
Table 47.
1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ mode.
t
t
t
t
t
t
LVDV
CLWH
NLNH
NLNH–PO
NLNH–A
OPR
Symbol
Symbol
CLCL
V
RESET
CC
is the period of CLKIN (PD1).
ALE Access Time from Power-down
Maximum Delay from
APD Enable to Internal PDN Valid Signal
Power-down timing
Reset (Reset) timing
RESET Active low Time
Power-on reset active low time
Warm reset
RESET high to operational device
Power-On Reset
V
t NLNH-PO
(2)
CC
(min)
Parameter
Parameter
(1)
t OPR
Using CLKIN (PD1)
Conditions
Conditions
Min
Warm Reset
t NLNH-A
t NLNH
Min
150
25
-70
1
15 * t
Max
DC and AC parameters
80
CLCL
Min
(1)
Max
120
-90
t OPR
Max
90
AI02866b
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Unit
Unit
ms
ns
µs
ns
µs
ns