psd835g2 STMicroelectronics, psd835g2 Datasheet - Page 20

• Manufacturer Part Number: psd835g2
• Description: Configurable Memory System On A Chip For 8-bit Microcontrollers
• Manufacturer: STMicroelectronics

PSD architectural overview
2.4
2.5
2.6
2.7
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I/O ports
The PSD has 52 I/O pins distributed over the seven ports (Port A, B, C, D, E, F and G). Each
I/O pin can be individually configured for different functions. ports can be configured as
standard MCU I/O ports, PLD I/O, or latched address outputs for MCUs using multiplexed
address/data buses.
The JTAG pins can be enabled on port E for in-system programming (ISP). ports F and G
can also be configured as data ports for a non-multiplexed bus.
Ports A and B can also be configured as a data port for a non-multiplexed bus.
MCU bus interface
PSD interfaces easily with most 8-bit MCUs that have either multiplexed or non-multiplexed
address/data buses. The device is configured to respond to the MCU’s control signals,
which are also used as inputs to the PLDs. For examples, please see
bus interface examples on page
Table 2.
Table 3.
JTAG port
In-system programming (ISP) can be performed through the JTAG signals on port E. This
serial interface allows complete programming of the entire PSD device. A blank device can
be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can
be multiplexed with other functions on port E.
JTAG pin assignments.
In-system programming (ISP)
Using the JTAG signals on port E, the entire PSD device (memory, logic, configuration) can
be programmed or erased without the use of the MCU.
Decode PLD (DPLD)
Complex PLD (CPLD)
Port E pins
PLD I/O
JTAG signals on port E
PE0
PE1
PE2
PE3
PE4
PE5
Name
68.
TMS
TCK
TDI
TDO
TSTAT
TERR
Inputs
Table 3: JTAG signals on port E
82
82
JTAG signal
Outputs
17
24
Section 16.3: MCU
Product terms
indicates the
PSD835G2
150
43