psd835g2 STMicroelectronics, psd835g2 Datasheet - Page 79
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psd835g2
Manufacturer Part Number
psd835g2
Description
Configurable Memory System On A Chip For 8-bit Microcontrollers
Manufacturer
STMicroelectronics
Datasheet
1.PSD835G2.pdf
(120 pages)
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PSD835G2
17.6
17.7
17.8
Table 16.
1. N/A = Not Applicable
Address In mode
For MCUs that have more than 16 address signals, the higher addresses can be connected
to port A, B, C, D or F and are routed as inputs to the PLDs. The address input can be
latched in the Input macrocell (IMC) by Address Strobe (ALE/AS, PD0). Any input that is
included in the DPLD equations for the SRAM, or primary or secondary Flash memory is
considered to be an address input.
Data port mode
Port F can be used as a data bus port for an MCU with a non-multiplexed address/data bus.
The Data port is connected to the data bus of the MCU. The general I/O functions are
disabled in port F if the port is configured as a Data port. Data port mode is automatically
configured in PSDsoft when a non-multiplexed bus MCU is selected.
Peripheral I/O mode
Peripheral I/O mode can be used to interface with external 8-bit peripherals. In this mode, all
of port F serves as a tri-state, bi-directional data buffer for the MCU. Peripheral I/O mode is
enabled by setting bit 7 of the VM register to a '1.'
directional buffer for the MCU data bus if Peripheral I/O mode is enabled. An equation for
PSEL0 and/or PSEL1 must be written in PSDsoft. The buffer is tri-stated when PSEL0 or
PSEL1 is not active.
All Other
8-Bit Multiplexed
8-Bit
Non-Multiplexed
Bus
MCU
I/O port latched address output assignments
(PE3-PE0)
Address
(A3-A0)
Port E
N/A
(PE7-PE4)
Address
(A7-A4)
Port E
N/A
(PF3-PF0)
Address
(A3-A0)
Port F
N/A
Figure 26
(PF7-PF4)
Address
(A7-A4)
Port F
N/A
shows how port A acts as a bi-
(1)
(continued)
(PG3-PG0)
Address
Address
(A3-A0)
(A3-A0)
Port G
(PG7-PG4)
Address
Address
(A7-A4)
(A7-A4)
Port G
I/O ports
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