psd835g2 STMicroelectronics, psd835g2 Datasheet - Page 53

• Manufacturer Part Number: psd835g2
• Description: Configurable Memory System On A Chip For 8-bit Microcontrollers
• Manufacturer: STMicroelectronics

PSD835G2
15
15.1
PLDs
The PLDs bring programmable logic functionality to the PSD. After specifying the logic for
the PLDs in PSDsoft, the logic is programmed into the device and available upon Power-up.
The PSD contains two PLDs: the Decode PLD (DPLD), and the Complex PLD (CPLD). The
PLDs are briefly discussed in the next few paragraphs, and in more detail in
Decode PLD (DPLD)
configuration of the PLDs.
The DPLD performs address decoding for Select signals for internal components, such as
memory, registers, and I/O ports.
The CPLD can be used for logic functions, such as loadable counters and shift registers,
state machines, and encoding and decoding logic. These logic functions can be constructed
using the 16 output macrocells (OMC), 24 input macrocells (IMC), and the AND Array. The
CPLD can also be used to generate External Chip Select (ECS0-ECS2) signals.
The AND Array is used to form product terms. These product terms are specified using
PSDsoft. An Input Bus consisting of 82 signals is connected to the PLDs. The signals are
shown in
PSD Turbo bit
The PLDs in the PSD can minimize power consumption by switching to standby when inputs
remain unchanged for an extended time of about 70ns. Resetting the Turbo bit to ’0’ (Bit 3 of
PMMR0) automatically places the PLDs into standby if no inputs are changing. Turning the
Turbo mode off increases propagation delays while reducing power consumption. See
Section 18: Power
Additionally, five bits are available in PMMR2 to block MCU control signals from entering the
PLDs. This reduces power consumption and can be used only when these MCU control
signals are not used in PLD logic equations.
Each of the two PLDs has unique characteristics suited for its applications. They are
described in the following sections.
Table 9.
MCU address bus
MCU control signals
Reset
Power-down
Port A input macrocells
Port B input macrocells
Port C input macrocells
Port D inputs
Table
DPLD and CPLD inputs
Input source
9.
(1)
management, on how to set the Turbo bit.
and
Section 15.3: Complex PLD (CPLD).Figure 12
CNTL2-CNTL0
Input name
PC7-PC0
PD3-PD0
PB7-PB0
PA7-PA0
A15-A0
PDN
RST
shows the
Section 15.2:
Number of
signals
16
3
1
1
8
8
8
4
53/120
PLDs