psd835g2 STMicroelectronics, psd835g2 Datasheet - Page 78

• Manufacturer Part Number: psd835g2
• Description: Configurable Memory System On A Chip For 8-bit Microcontrollers
• Manufacturer: STMicroelectronics

I/O ports
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Table 14.
1. Can be multiplexed with other I/O functions.
Table 15.
1. N/A = Not Applicable
2. Control register setting is not applicable to ports A, B and C.
3. The direction of the port A,B,C, and F pins are controlled by the Direction register ORed with the individual
4. Any of these three methods enables the JTAG pins on port E.
Table 16.
Address Out
Address In
Data port
Peripheral I/O
JTAG ISP
8051XA
80C251
(Page mode)
Data port (Port F)
(Port A,B,C,D, F)
Peripheral I/O
(Port E, F, G)
Address Out
output enable product term (.oe) from the CPLD AND Array.
JTAG ISP
Address In
MCU I/O
PLD I/O
(Port F)
Mode
Port mode
MCU
(4)
Port operating modes (continued)
Port operating mode settings
I/O port latched address output assignments
Defined in PSDsoft
Declare pins or logic
equations for input
(PE3-PE0)
Selected for MCU
with non-mux bus
Declare pins only
Declare pins only
Declare pins only
Declare pins and
Logic equations
logic equations
Port E
(PSEL0 & 1)
N/A
N/A
macrocells
Port A
Yes
No
No
No
No
(PE7-PE4)
Address
Port B
(A7-A4)
Port E
Yes
No
No
No
No
N/A
register
Control
setting
Port C
N/A
N/A
N/A
N/A
N/A
0
Yes
1
No
No
No
No
(2)
(PF3-PF0)
(1)
Port F
N/A
N/A
Port D
1 = output,
Direction
Yes
0 = input
No
No
No
No
register
setting
N/A
N/A
N/A
N/A
1
(3)
(3)
(3)
(PF7-PF4)
Address
(A7-A4)
Port F
N/A
Yes (A7-
Port E
(1)
Yes
A0)
No
No
No
VM register
PIO bit = 1
(1)
setting
N/A
N/A
N/A
N/A
N/A
N/A
(PG3-PG0)
(A11-A8)
(A11-A8)
Address
Address
Port G
Yes (A7-
Port F
A0)
Yes
Yes
Yes
No
JTAG_Enable
JTAG enable
PSD835G2
(PG7-PG4)
(A15-A12)
N/A
N/A
N/A
N/A
N/A
N/A
Address
Address
(A15-A8)
(A7-A4)
Yes (A7-
Port G
Port G
A0) or
No
No
No
No