psd835g2 STMicroelectronics, psd835g2 Datasheet - Page 19

• Manufacturer Part Number: psd835g2
• Description: Configurable Memory System On A Chip For 8-bit Microcontrollers
• Manufacturer: STMicroelectronics

PSD835G2
2
2.1
2.2
2.3
PSD architectural overview
PSD devices contain several major functional blocks.
the architecture of the PSD device family. The functions of each block are described briefly
in the following sections. Many of the blocks perform multiple functions and are user
configurable.
Memory
Each of the memory blocks is briefly discussed in the following paragraphs. A more detailed
discussion can be found in the section entitled
4 Mbit (512K x 8) Flash memory is the primary memory of the PSD. It is divided into 8
equally-sized sectors that are individually selectable.
The 256 Kbit (32K x 8) secondary Flash memory is divided into 4 equally-sized sectors.
Each sector is individually selectable.
The 64 Kbit SRAM is intended for use as a scratch-pad memory or as an extension to the
MCU SRAM.
Each sector of memory can be located in a different address space as defined by the user.
The access times for all memory types includes the address latching and DPLD decoding
time.
Page register
The 8-bit Page register expands the address range of the MCU by up to 256 times. The
paged address can be used as part of the address space to access external memory and
peripherals, or internal memory and I/O. The Page register can also be used to change the
address mapping of sectors of the Flash memories into different memory spaces for IAP.
PLDs
The device contains two PLDs, the Decode PLD (DPLD) and the Complex PLD (CPLD), as
shown in
PLDs reduces power consumption, optimizes cost/performance, and eases design entry.
The DPLD is used to decode addresses and to generate Sector Select signals for the PSD
internal memory and registers. The CPLD can implement user-defined logic functions. The
DPLD has combinatorial outputs. The CPLD has 16 output macrocells (OMC) and 8
combinatorial outputs. The PSD also has 24 input macrocells (IMC) that can be configured
as inputs to the PLDs. The PLDs receive their inputs from the PLD Input Bus and are
differentiated by their output destinations, number of product terms, and macrocells.
The PLDs consume minimal power by using power-management design techniques. The
speed and power consumption of the PLD is controlled by the Turbo bit in PMMR0 and other
bits in the PMMR2. These registers are set by the MCU at run-time. There is a slight penalty
to PLD propagation time when invoking the power management features.
Table
2, each optimized for a different function. The functional partitioning of the
Section 6.1: Memory blocks on page
Figure 2: PSD block diagram
PSD architectural overview
shows
32. The
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