psd835g2 STMicroelectronics, psd835g2 Datasheet - Page 105

• Manufacturer Part Number: psd835g2
• Description: Configurable Memory System On A Chip For 8-bit Microcontrollers
• Manufacturer: STMicroelectronics

PSD835G2
Table 37.
1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
Table 38.
1. Fast Slew Rate output available on ports C and F.
2. CLKIN (PD1) t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
Symbol
Symbol
PD
EA
ER
ARP
ARPW
ARD
MAX
S
H
CH
CL
CO
ARD
MIN
CPLD input pin/feedback to
CPLD combinatorial output
CPLD input to CPLD output
enable
CPLD input to CPLD output
disable
CPLD register clear or preset
delay
CPLD register clear or preset
pulse Width
CPLD array delay
Maximum frequency
external feedback
Maximum frequency
internal feedback (f
Maximum frequency
pipelined data
Input setup time
Input hold time
Clock high time
Clock low time
Clock to Output Delay
CPLD array delay
Minimum clock period
CPLD combinatorial timing
CPLD macrocell synchronous clock mode timing
CLCL
Parameter
Parameter
= t
CH
+ t
CL
CNT
.
(2)
)
Any macrocell
1/(t
Conditions
Clock Input
Clock Input
Clock Input
1/(t
1/(t
Any macrocell
t
S
CH
Conditions
+t
CH
S
+t
+t
CO
+t
CO
CL
–10)
CL
)
)
Min
14
12
0
6
6
Min
10
-70
Max
34.4
52.6
83.3
-70
15
11
Max
20
21
21
21
11
Min
15
10
10
20
0
Min
20
-90
-90
30.30
43.48
50.00
Max
18
16
Max
25
26
26
26
16
Aloc
Aloc
+ 2
+ 2
PT
+ 2
+ 2
PT
DC and AC parameters
Turbo
Turbo
+ 12
Off
+ 12
+ 12
+ 12
+ 12
+ 12
Off
Slew
rate
Slew
– 2
rate
(1)
– 2
– 2
– 2
– 2
(1)
105/120
MHz
MHz
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns