psd835g2 STMicroelectronics, psd835g2 Datasheet - Page 86

• Manufacturer Part Number: psd835g2
• Description: Configurable Memory System On A Chip For 8-bit Microcontrollers
• Manufacturer: STMicroelectronics

I/O ports
17.24
17.25
86/120
Port F – functionality and structure
Port F can be configured to perform one or more of the following functions:
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Port G – functionality and structure
Port G can be configured to perform one or more of the following functions:
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MCU I/O mode
CPLD Output – External Chip Select ECS7-ECS0 can be connected to port F (or port
C).
CPLD Input – as direct input of the CPLD array.
Address In – addition high address inputs. Direct input to the CPLD array, no Input
macrocell (IMC) latching is available.
Latched Address Out – Provide latched address out per
Up Reset, Warm Reset and Power-down
Slew Rate – pins can be set up for fast slew rate.
Data port – connected to D7-D0 when port F is configured as Data port for a non-
multiplexed bus.
Peripheral I/O mode.
MCU I/O mode
Latched Address Out – Provide latched address out per
Open Drain – pins can be configured in Open Drain mode.
mode.
Table 26: Status during Power-
Table
26.
PSD835G2