psd835g2 STMicroelectronics, psd835g2 Datasheet - Page 85

• Manufacturer Part Number: psd835g2
• Description: Configurable Memory System On A Chip For 8-bit Microcontrollers
• Manufacturer: STMicroelectronics

PSD835G2
17.22
Figure 28. Port D structure
17.23
Port D – functionality and structure
Port D has four I/O pins. It can be configured to program one or more of the following
functions (see
Port D pins can be configured in PSDsoft as input pins for other dedicated functions:
●
●
●
●
Port E – functionality and structure
Port E can be configured to perform one or more of the following functions:
●
●
●
●
WR
WR
–
–
PD0 – ALE, as Address Strobe input.
PD1 – CLKIN, as Clock input to the macrocell flip-flops and APD counter.
PD2 – CSI, as active low Chip Select input. A high input will disable the Flash/SRAM
memories and the CSIOP.
PD3 – as DBE input from 68HC912.
MCU I/O mode
In-System Programming – JTAG port can be enabled for programming/erase of the
PSD device. Refer to
for more information.
Open Drain – port E pins can be configured in Open Drain mode.
Latched Address Output – Provided latched address (A7-A0) output.
MCU I/O mode
CPLD Input – direct input to CPLD, no Input macrocell (IMC).
READ MUX
DATA OUT
Figure
DIR REG.
D
D
REG.
P
D
B
Q
Q
28):
Section 20: Programming in-circuit using the JTAG/ISP interface
DATA IN
CPLD-INPUT
DATA OUT
OUTPUT
OUTPUT
SELECT
MUX
PORT D PIN
I/O ports
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