at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 85
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at85c51snd3
Manufacturer Part Number
at85c51snd3
Description
At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
Manufacturer
ATMEL Corporation
Datasheet
1.AT85C51SND3.pdf
(271 pages)
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USB Controller
Description
USB Connection
7632D–MP3–01/07
The AT85C51SND3B derivatives implement a USB controller allowing the
AT85C51SND3B to act as a USB device or a USB host.
The main features of the USB controller:
•
•
•
•
•
The C51 core interfaces with the USB Controller using a set of special function registers
detailed in Table 49, page 40.
As shown in Figure 49, the USB controller is based on seven functional blocks:
•
•
•
•
•
•
•
Figure 49. USB Controller Block Diagram
Figure 50 shows the connection of the AT85C51SND3B to the USB connector and the
the connection of the RC filter to the UBIAS pin. DPF and DMF pins are connected
through 2 termination resistors.
Value of all discrete components is detailed in the Section “DC Characteristics”,
page 242.
CLOCK
Full-speed and high-speed device.
Full-speed host with OTG compliance.
Automatic Data Flow Controller (DFC) transfer without CPU support.
2368 bytes of DPRAM.
Up to 7 endpoints/pipes
–
–
–
the PLL clock (see Section “Clock Generator”, page 29) which delivers 480 MHz
clock for USB high-speed mode support.
the USB HS/FS pad supporting speed negotiation, attach/detach and data transfer
the USB OTG pad supporting OTG negotiation
the device controller allowing AT85C51SND3B to act as a device
the host controller allowing AT85C51SND3B to act as a device
the 2368-byte dual port RAM for endpoints and pipes memory
the interrupt controller
PLL
CPU
DFC
Bus
Bus
1 endpoint of 64 bytes (default control),
2 endpoints of 512 bytes max, (one or two banks),
4 endpoints of 64 bytes max, (one or two banks).
2368 Bytes
DPRAM
Device Controller
Host Controller
Controller
Interrupt
Interrupt
Request
USB
High Speed
Full Speed
USB Pad
USB Pad
OTG
UVCC
UVCON
UID
DMF
DPF
DMH
DPH
UBIAS
85
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