at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 58

• Manufacturer Part Number: at85c51snd3
• Description: At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

External Interrupts
INT1:0 Inputs
KIN3:0 Inputs
Input Sampling
58
AT85C51SND3B
External interrupts INT0 and INT1 (INTn, n = 0 or 1) pins may each be programmed to
be level-triggered or edge-triggered, dependent upon bits IT0 and IT1 (ITn, n = 0 or 1) in
TCON register as shown in INT1:0 Input Circuitry. If ITn = 0, INTn is triggered by a low
level at the pin. If ITn = 1, INTn is negative-edge triggered. External interrupts are
enabled with bits EX0 and EX1 (EXn, n = 0 or 1) in IEN0. Events on INTn set the inter-
rupt request flag IEn in TCON register. If the interrupt is edge-triggered, the request flag
is cleared by hardware when vectoring to the interrupt service routine. If the interrupt is
level-triggered, the interrupt service routine must clear the request flag and the interrupt
must be de-asserted before the end of the interrupt service routine.
INT0 and INT1 inputs provide both the capability to exit from Power-down mode on low
level signals as detailed in Section “Exiting Power-down Mode”, page 22.
Figure 29. INT1:0 Input Circuitry
External interrupts KIN0 to KIN3 provide the capability to connect a matrix keyboard. For
detailed information on these inputs, refer to Section “Keyboard Interface”, page 240.
External interrupt pins (INT1:0 and KIN3:0) are sampled once per peripheral cycle (6
peripheral clock periods) (see Minimum Pulse Timings). A level-triggered interrupt pin
held low or high for more than 6 peripheral clock periods (12 oscillator in standard mode
or 6 oscillator clock periods in X2 mode) guarantees detection. Edge-triggered external
interrupts must hold the request pin low for at least 6 peripheral clock periods.
Figure 30. Minimum Pulse Timings
INT0/1
Level-Triggered Interrupt
Edge-Triggered Interrupt
TCON.0/2
IT0/1
0
1
1 cycle
> 1 Peripheral Cycle
TCON.1/3
> 1 Peripheral Cycle
IE0/1
1 cycle
1 cycle
IEN0.0/2
EX0/1
INT0/1
Interrupt
Request
7632D–MP3–01/07