at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 145

• Manufacturer Part Number: at85c51snd3
• Description: At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

7632D–MP3–01/07
Table 148. UPINTX Register
UPINTX (1.C8h) – USB Pipe Interrupt Register
FIFOCON
Number
Bit
7
7
6
5
4
3
2
1
RXSTALLI /
Mnemonic Description
FIFOCON
CRCERR
NAKEDI
NAKEDI
TXOUTI
TXSTPI
PERRI
RWAL
Bit
6
FIFO Control
For OUT and SETUP Pipe:
Set by hardware when the current bank is free, at the same time than TXOUT or
TXSTP.
Clear to send the FIFO data and to switch the bank. Setting by software has no
effect.
For IN Pipe:
Set by hardware when a new IN message is stored in the current bank, at the
same time than RXIN.
Clear to free the current bank and to switch to the following bank. Setting by
software has no effect.
NAK Handshake received
Set by hardware when a NAK has been received on the current bank of the Pipe.
This triggers an interrupt if the NAKEDE bit is set in the UPIENX register.
Shall be clear to handshake the interrupt. Setting by software has no effect.
Read/Write Allowed
OUT Pipe:
Set by hardware when the firmware can write a new data into the Pipe FIFO.
Cleared by hardware when the current Pipe FIFO is full.
IN Pipe:
Set by hardware when the firmware can read a new data into the Pipe FIFO.
Cleared by hardware when the current Pipe FIFO is empty.
This bit is also cleared by hardware when the RXSTALL or the PERR bit is set
PIPE Error
Set by hardware when an error occurs on the current bank of the Pipe. This
triggers an interrupt if the PERRE bit is set in the UPIENX register. Refers to the
UPERRX register to determine the source of the error.
Automatically cleared by hardware when the error source bit is cleared.
SETUP Bank ready
Set by hardware when the current SETUP bank is free and can be filled. This
triggers an interrupt if the TXSTPE bit is set in the UPIENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
OUT Bank ready
Set by hardware when the current OUT bank is free and can be filled. This
triggers an interrupt if the TXOUTE bit is set in the UPIENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
STALL Received / Isochronous CRC Error
Set by hardware when a STALL handshake has been received on the current
bank of the Pipe. The Pipe is automatically frozen. This triggers an interrupt if the
RXSTALLE bit is set in the UPIENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
For Isochronous Pipe:
Set by hardware when a CRC error occurs on the current bank of the Pipe. This
triggers an interrupt if the TXSTPE bit is set in the UPIENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
RWAL
5
PERRI
4
TXSTPI
3
TXOUTI
2
RXSTALLI
1
RXINI
0
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