at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 81

• Manufacturer Part Number: at85c51snd3
• Description: At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

Data Flow Configuration
Interrupts
7632D–MP3–01/07
Figure 46. Immediate Data Flow Abort Diagram
Figure 47. Delayed Data Flow Abort Diagram
Prior to any operation, the DFC must be configured in term of clock source and channel
priority, then DFC can be enabled.
Each time a data flow must be established, a data flow descriptor must be written to the
DFC.
As shown in Figure 48, the DFC interrupt request is generated by 2 different sources:
the EOFI0 flag or EOFI1 flag in DFCSTA. Both sources can be enabled separately by
using the EOFE0 and EOFE1 bits in DFCCON. A global enable of the DFC interrupt is
provided by setting the EDFC bit in IENx register.
The interrupt is requested each time one of the 2 sources is asserted.
EOFI0 or EOFI1 flags are set:
•
•
•
Note:
EOFI0 and EOFI1 flags must be cleared by software by setting EOFIA0 and EOFIA1
bits in DFCCON, in order to acknowledge the interrupt. Setting these flags by software
has no effect.
Figure 48. DFC Interrupt System
Remaining DP
Remaining DP
at the end of a data flow on respective channel.
after an immediate abort command at the end of the byte transfer.
after a delayed abort at the end of the data packet transfer.
Data bus
Data bus
DFBSYx
DFBSYx
DFABTx
DFABTx
An abort command never sets flags while in the process of writing DFD.
DFCSTA.1
DFCSTA.5
EOFI0
EOFI1
N+2
N+2
N+1
DP
N+1
DP
DP
N
DFCCON.2
DFCCON.6
EOFE0
EOFE1
N
EDFC
IENx.y
DFC
Interrupt
Request
81