at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 25

• Manufacturer Part Number: at85c51snd3
• Description: At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

Cold Reset
Warm Reset
Watchdog Timer Reset
Power Fail Detector
7632D–MP3–01/07
Figure 13. Reset Circuitry and Power-On Reset
2 conditions are required before enabling a CPU start-up:
•
•
If one of these 2 conditions are not met, the microcontroller does not start correctly and
can execute an instruction fetch from anywhere in the program space. An active level
applied on the RST pin must be asserted till both of the above conditions are met. A
reset is active when the level V
of time where V
into account to determine the reset pulse width:
•
•
To determine the capacitor value to implement, the highest value of these 2 parameters
has to be chosen.
To achieve a valid reset, the reset signal must be maintained for at least 2 machine
cycles (24 oscillator clock periods) while the oscillator is running. The number of clock
periods is mode independent (X2 or X1).
As detailed in Section “Watchdog Timer”, page 75, the WDT generates a 96-clock
period pulse on the RST pin. In order to properly propagate this pulse to the rest of the
application in case of external capacitor or power-supply supervisor circuit, a 1 kΩ resis-
tor must be added as shown in Figure 14.
Figure 14. Reset Circuitry for WDT Reset-out Usage
The Power Fail Detector (PFD) ensures that whole product is in reset when internal volt-
age is out of its limits specification. PFD limits are detailed in the Section “DC
Characteristics”, page 242.
V
The level on X1 input pin must be outside the specification (V
V
Oscillator startup time.
RST
DD
DD
must reach the specified V
rise time,
IOVSS
IOVDD
IOVSS
RST input circuitry
DD
+
N
R
and the oscillator are not stabilized. 2 parameters have to be taken
RST
1K
IL
RST
is reached and when the pulse width covers the period
DD
range
IOVDD
IOVSS
N
R
RST
To CPU Core
and Peripherals
From Internal
Reset Source
IH
Power-on Reset
, V
IOVSS
To Other
On-board
Circuitry
To CPU Core
and Peripherals
From WDT
Reset Source
IL
)
+
RST
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