at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 83
at85c51snd3
Manufacturer Part Number
at85c51snd3
Description
At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
Manufacturer
ATMEL Corporation
Datasheet
1.AT85C51SND3.pdf
(271 pages)
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7632D–MP3–01/07
Reset Value = 0000 0000b
Table 96. DFCCON Register
DFCCON (1.85h) – DFC Channel Control Register
Reset Value = 0000 0000b
Number
DFABT1
Number
Bit
Bit
3
2
1
0
7
7
6
5
4
3
2
1
0
Mnemonic Description
Mnemonic Description
DFBSY0
DFABT1
DFABT0
EOFIA1
EOFIA0
DRDY0
SRDY0
EOFE1
EOFE1
EOFE0
EOFI0
Bit
Bit
6
-
-
Channel 0 Destination Ready Flag
Set by hardware when the destination peripheral of channel 0 is ready.
Cleared by hardware when the destination peripheral of channel 0 is not ready.
Channel 0 Source Ready Flag
Set by hardware when the source peripheral of channel 0 is ready.
Cleared by hardware when the source peripheral of channel 0 is not ready.
Channel 0 End Of Data Flow Interrupt Flag
Set by hardware at the end of a channel 0 data flow transfer.
Cleared by software by setting EOFIA0 in DFCCON. Can not be set by software.
Channel 0 Busy Flag
Set by hardware when a transfer is on-going on channel 0.
Cleared by hardware when no transfer is on-going on channel 0.
Channel 1 Abort Control Bit
Set to trigger an abort on channel 1.
This bit is cleared by hardware.
Channel 1 End Of Data Flow Interrupt Enable Bit
Set to enable channel 1 EOF interrupt.
Clear to disable channel 1 EOF interrupt.
Channel 1 End Of Flow Interrupt Acknowledge Bit
Set to acknowledge the channel 1 EOF interrupt (clear EOFI1 flag).
Clearing this bit has no effect.
The value read from this bit is always 0.
Reserved
The value read from this bit is always 0. Do not set this bit.
Channel 0 Abort Control Bit
Set to trigger an abort on channel 0.
This bit is cleared by hardware.
Channel 0 End Of Data Flow Interrupt Enable Bit
Set to enable channel 0 EOF interrupt.
Clear to disable channel 0 EOF interrupt.
Channel 0 End Of Flow Interrupt Acknowledge Bit
Set to acknowledge the channel 0 EOF interrupt (clear EOFI0 flag).
Clearing this bit has no effect.
The value read from this bit is always 0.
Reserved
The value read from this bit is always 0. Do not set this bit.
EOFIA1
5
4
-
DFABT0
3
EOFE0
2
EOFIA0
1
0
-
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