at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 219

• Manufacturer Part Number: at85c51snd3
• Description: At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

Receiver Errors
Framing Error
Parity Error
Overrun Error
Transmitter
Flow Control
Interrupts
7632D–MP3–01/07
There are three kinds of errors that can be set during character reception: the framing
error, the parity error, and the overrun error detailed in the following sections.
A framing error occurs when the stop field of a received character is not at high level.
Framing error is reported in FEI flag in SINT. Framing error condition is acknowledged
by clearing the FEI flag.
A parity error occurs when the parity field of a received character does not matches the
programmed one in PMOD1:0 bits. Parity error is reported in PEI flag in SINT. Parity
error condition is acknowledged by clearing the PEI flag.
An overrun error occurs when a character is received while the Rx shift register is full
(Rx FIFO full). In this case, received character is discarded. Overrun error is reported in
OEI flag in SINT. Overrun error condition is acknowledged by clearing the OEI flag.
Note:
As shown in Figure 112, the transmitter is based on a character handler taking care of
character transmission and fed by the transmission shift register filled itself by a 1-byte
data FIFO managed by the FIFO and flow controller.
Figure 112. Transmitter Block Diagram
The transmission flow can be controlled by hardware using the CTS pin controlled by
the external receiver. The goal of the flow control is to stop transmission when the
receiver is full of data. CTS usage and so associated flow control is enabled using
CTSEN bit in SFCON.
The transmitter stop latency may vary from 0 to a maximum of 1 character, meaning that
transmission always stops at the end of the character under transmission if any.
As shown in Figure 113, the SIO implements five interrupt sources reported in RI, TI,
FEI, PEI, OEI and EOTI flags in SINT. These flags are detailed in the previous sections.
These sources are enabled separately using RIE, TIE, FEIE, PEIE, OEIE and EOTIE
enable bits respectively in SIEN.
The interrupt request is generated each time an enabled source flag is set, and the glo-
bal SIO interrupt enable bit is set (ES in IEN0 register).
In case of data burst reception, the error flags report an error within the data burst. It is
obvious to discard the whole data burst and to handle the errors by the protocol (retry…).
CLOCK
BRG
1-byte FIFO
Tx Shift Reg
SBUF Tx
SCON.1:0
GBIT1:0
SINT.0
TI
FIFO & Flow Controller
Character Handler
SINT.5
EOTI
CTSEN
SCON.3
CTS
TXD
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