at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 206

• Manufacturer Part Number: at85c51snd3
• Description: At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

206
AT85C51SND3B
Table 227. MMINT Register
MMINT (1.BEh Read Only) – MMC Interrupt Register
Reset Value = 0000 0000b
Table 228. MMMSK Register
MMMSK (1.BFh) – MMC Interrupt Mask Register
Number
Number
MCBM
CDETI
Bit
Bit
7
7
6
5
4
3
2
1
0
7
7
Mnemonic Description
Mnemonic Description
CDETM
CDETI
EORM
EORI
EORI
EOCI
WFRI
EOFI
HFRI
EOBI
Bit
Bit
6
6
-
Card Detection Interrupt Flag
Set by hardware every time CDET bit in MMSTA is toggling.
Cleared when reading MMINT.
End of Response Interrupt Flag
Set by hardware at the end of response reception.
Cleared when reading MMINT.
End of Command Interrupt Flag
Set by hardware at the end of command transmission.
Cleared when reading MMINT.
End of Frame Interrupt Flag
Set by hardware at the end of frame (stream, single block or multi block) transfer.
Clear when reading MMINT.
Whole FIFO Ready Interrupt Flag
Set by hardware when 16 bytes can be read in receive mode or written in
transmit mode.
Cleared when reading MMINT.
Half FIFO Ready Interrupt Flag
Set by hardware when 8 bytes can be read in receive mode or written in transmit
mode.
Cleared when reading MMINT.
End of Block Interrupt Flag
Set by hardware at the end of block (single block or multi block) transfer.
Cleared when reading MMINT.
Reserved
The value read from this bit is always 0. Do not set this bit.
Card Detection Interrupt Mask Bit
Set to prevent CDETI flag from generating an interrupt.
Clear to allow CDETI flag to generate an interrupt.
EOCM
EOCI
5
5
EOFM
EOFI
4
4
WFRM
WFRI
3
3
HFRM
HFRI
2
2
EOBM
EOBI
1
1
7632D–MP3–01/07
0
0
-
-