at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 203

• Manufacturer Part Number: at85c51snd3
• Description: At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

Registers
7632D–MP3–01/07
Table 222. MMCON0 Register
MMCON0 (1.B1h) – MMC Control Register 0
Reset Value = 0000 0010b
Table 223. MMCON1 Register
MMCON1 (1.B2h) – MMC Control Register 1
Number
Number
BLEN3
7-4
Bit
Bit
7
7
6
5
4
3
2
1
0
7
3
-
Mnemonic Description
Mnemonic Description
BLEN11:8
MBLOCK
CRCDIS
DATDIR
DPTRR
DPTRR
CRPTR
CTPTR
BLEN2
DFMT
RFMT
Bit
Bit
6
6
-
Reserved
The value read from this bit is always 0. do not set this bit
Data Pointer Reset Bit
Set to reset the read and write pointer of the data FIFO.
Cleared by hardware after pointer reset is achieved.
Command Receive Pointer Reset Bit
Set to reset the read pointer of the receive command FIFO.
Cleared by hardware after pointer reset is achieved.
Command Transmit Pointer Reset Bit
Set to reset the write pointer of the transmit command FIFO.
Cleared by hardware after pointer reset is achieved.
Multi-block Enable Bit
Set to select multi-block data format.
Clear to select single block data format.
Data Format Bit
Set to select the block-oriented data format.
Clear to select the stream data format.
Response Format Bit
Set to select the 48-bit response format.
Clear to select the 136-bit response format.
Clear to enable the CRC7 computation when receiving a response.
Block Length Bits
Refer to Table 221 for bits description.
Data Direction Bit
Set to select data transfer from host to card (write mode).
Clear to select data transfer from card to host (read mode).
CRC7 Disable Bit
Set to disable the CRC7 computation when receiving a response.
CRPTR
BLEN1
5
5
CTPTR
BLEN0
4
4
MBLOCK
DATDIR
3
3
DATEN
DFMT
2
2
RESPEN
RFMT
1
1
CRCDIS
CMDEN
0
0
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