at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 173

• Manufacturer Part Number: at85c51snd3
• Description: At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

“Read” Session
“Write” Session
NFCE Signal Force Low
Data Transfer Stop
Column Address Extension
7632D–MP3–01/07
Table 194. Device Selection Allowed Configuration
A “read” session is launched and the DFC flow control is enabled. When processing the
spare zone, its information will be checked.
A “write” session is launched and the DFC flow control is enabled. When processing the
spare zone, its information will be set.
The 512B-pages memories need to keep asserted the NFCE line during the access time
of a data. This can be done by setting the CELOW bit. In this case, the NFCEx signal
selected by the last ‘device select’ action is asserted (NFCE[DEV]= L).
If a new ‘device select’ action occurs while the CELOW bit is set, the NFCEx signal of
the old selected device is de-asserted (NFCE[OLD_DEV]= H), and the NFCEx signal of
the new one is asserted (NFCE[NEW_DEV]= L).
Clearing the CELOW bit does not force the NFCE signal high:
•
•
This action stops the NFC when the data transfer is finished. In this case, the controller
state becomes “not running” (NFRUN bit cleared). This can also be used as an abort
signal in streaming mode.
The 512B-pages memories have different kind of read commands (00h, 01h, 50h)
depending the data zone that need to be processed (1st half, 2nd half or spare). The
column address given is relative to the zone chosen by the read command. The NFC
needs to have the absolute column address to stop automatically at the end of the page.
The column address extension is given thanks to that command. A9:8 holds the address
extension.
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•
•
SMCEN
The NFCE signal is automatically asserted at the beginning of the execution of any
new commands.
The NFCE signal is automatically de-asserted at the completion of the commands.
00h selects the 1st half zone, i.e. the 0-255 range in the data zone. This is the
default value. A read or a write in NFADC resets A9:8 to 00h.
01h selects the 2nd half zone, i.e. the 256-511 range in the data zone.
10h selects the spare zone, i.e. the 512-527 range in the data zone.
0
1
NUMDEV
0
1
2
3
0
1
2
3
3 (SMC), 0, 1, 2
Allowed DEV
3 (SMC), 0, 1
3 (SMC), 0
0, 1, 2, 3
3 (SMC)
0, 1, 2
0, 1
0
Comment
No NF memory is selected
The SMLCK signal can not be used in this configuration,
the SMLCK bit is irrelevant.
Neither SMLCK nor SMINS signals can be used in this
configuration. SMCD and SMLCK bits have an irrelevant
value. SMCTE shall be cleared.
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