at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 51

• Manufacturer Part Number: at85c51snd3
• Description: At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

Upper 128 Bytes
XDATA Segment
Memory Configuration
7632D–MP3–01/07
Table 63. Register Bank Selection
The next 16 Bytes above the register banks form a block of bit-addressable memory
space. The C51 instruction set includes a wide selection of single-bit instructions, and
the 128 bits in this area can be directly addressed by these instructions. The bit
addresses in this area are 00h to 7Fh.
Figure 26. Lower 128 Bytes Internal RAM Organization
The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect
addressing mode. Using direct addressing mode within this address range selects the
Special Function Registers, SFRs. For information on this segment, refer to the
Section “Special Function Registers”, page 37.
The on-chip expanded RAM (XRAM) are accessible using indirect addressing mode
through MOVX instructions.
As shown in Figure 25, the 64KB addressing space of the C51 is artificially increased by
usage of logical address over a physical one. For example, the boot memory which con-
tains the bootstrap software is implemented at physical address 10000h but is starting at
logical address code 0000h which means that the bootstrap is first executed when a
system reset occurs.
To achieve such logical mapping over the physical memory, some registers have been
implemented to give the base address of the memory segments and their size:
•
•
•
•
•
The data segment is not programmable in size as it is a fixed 256-byte segment.
MEMCBAX (see Table 65) for the code segment base address.
MEMDBAX (see Table 66) for the data segment base address.
MEMXBAX (see Table 67) for the xdata segment base address.
MEMCSX (see Table 68) for the code segment size.
MEMXSX (see Table 69) for the code segment size.
RS1
0
0
1
1
RS0
0
1
0
1
30h
20h
18h
10h
08h
00h
Description
Register bank 0 from 00h to 07h
Register bank 1 from 08h to 0Fh
Register bank 2 from 10h to 17h
Register bank 3 from 18h to 1Fh
7Fh
2Fh
1Fh
17h
0Fh
07h
Bit-Addressable Space
(Bit Addresses 0-7Fh)
4 Banks of
8 Registers
R0-R7
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