at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 232

• Manufacturer Part Number: at85c51snd3
• Description: At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

232
AT85C51SND3B
Reset Value = 0001 0100b
Table 253. SPSCR Register
SPSCR (1.92h) – SPI Status and Control Register
Number
Number
SPIF
1-0
Bit
Bit
4
3
2
7
7
6
5
4
3
2
Mnemonic Description
Mnemonic Description
UARTM
SPR1:0
MODF
MSTR
CPOL
CPHA
SPTE
SPIF
OVR
Bit
Bit
6
-
-
Master Mode Select
Set to select the master mode.
Clear to select the slave mode.
SPI Clock Polarity Bit
Set to have the clock output set to high level in idle state.
Clear to have the clock output set to low level in idle state.
SPI Clock Phase Bit
Set to have the data sampled when the clock returns to idle state (see CPOL).
Clear to have the data sampled when the clock leaves the idle state (see CPOL).
SPI Rate Bits 0 and 1
Refer to Table 251 for bit rate description.
SPI Interrupt Flag
Set by hardware when an 8-bit shift is completed.
Cleared by hardware to indicate data transfer is in progress or has been
acknowledged by a clearing sequence: reading or writing SPDAT after reading
SPSCR.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Overrun Error Flag
Set by hardware when a byte is received whereas SPIF is set (the previous
received data is not overwritten).
Cleared by hardware when reading SPSCR.
Mode Fault Interrupt Flag
Set by hardware to indicate that the SS pin is in inappropriate logic level.
Cleared by hardware when reading SPSCR
When MODF error occurred:
- In slave mode: SPI interface ignores all transmitted data while SS remains high.
A new transmission is perform as soon as SS returns low.
- In master mode: SPI interface is disabled (SPEN=0, see description for SPEN
bit in SPCON register).
Serial Peripheral Transmit register Empty Interrupt Flag
Set by hardware when transmit register is empty (if needed, SPDAT can be
loaded with another data).
Cleared by hardware when transmit register is full (no more data should be
loaded in SPDAT).
Serial Peripheral UART mode
Set to select UART mode: data is transmitted LSB first.
Clear to select SPI mode: data is transmitted MSB first.
OVR
5
MODF
4
SPTE
3
UARTM
2
SPTEIE
1
7632D–MP3–01/07
MODFIE
0