at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 130

• Manufacturer Part Number: at85c51snd3
• Description: At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

USB Reset
Address Setup
Remote Wake-Up
Detection
USB Pipe Reset
Pipe Data Access
Control Pipe
Management
130
AT85C51SND3B
The USB controller sends a USB Reset when the firmware set the RESET bit. The RSTI
bit is set by hardware when the USB Reset has been sent. This triggers an interrupt if
the RSTE has been set.
When a USB Reset has been sent, all the Pipe configuration and the memory allocation
are reset. The General Host interrupt enable register is left unchanged.
If the bus was previously in suspend mode (SOFE = 0), the USB controller automatically
switches to the resume mode (HWUPI is set) and the SOFE bit is set by hardware in
order to generate SOF immediately after the USB Reset.
Once the Device has answer to the first Host requests with the default address (0), the
Host assigns a new address to the device. The Host controller has to send a USB reset
to the device and perform a SET ADDRESS control request, with the new address to be
used by the Device. This control request ended, the firmware write the new address into
the UHADDR register. All following requests, on every Pipes, will be performed using
this new address.
When the Host controller send a USB reset, the UHADDR register is reset by hardware
and the following Host requests will be performed using the default address (0).
The Host Controller enters in Suspend mode when clearing the SOFE bit. No more Start
Of Frame is sent on the USB bus and the USB Device enters in Suspend mode 3ms
later.
The Device awakes the Host Controller by sending an Upstream Resume (Remote
Wake-Up feature). The Host Controller detects a non-idle state on the USB bus and set
the HWUPI bit. If the non-Idle correspond to an Upstream Resume (K state), the
RXRSMI bit is set by hardware. The firmware has to generate a downstream resume
within 1ms and for at least 20ms by setting the RESUME bit.
Once the downstream Resume has been generated, the SOFE bit is automatically set
by hardware in order to generate SOF immediately after the USB resume.
The firmware can reset a Pipe using the pipe reset register. The configuration of the
pipe and the data toggle remains unchanged. Only the bank management and the sta-
tus bits are reset to their initial values.
To completely reset a Pipe, the firmware has to disable and then enable the pipe.
In order to read or to write into the Pipe Fifo, the CPU selects the Pipe number with the
UPNUM register and performs read or write action on the UPDATX register.
A Control transaction is composed of 3 phases:
•
•
•
SETUP
Data (IN or OUT)
Status (OUT or IN)
Ready
Host
or HWUP=1
SOFE=1
SOFE=0
Suspend
Host
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