at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 212

• Manufacturer Part Number: at85c51snd3
• Description: At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

Registers
212
AT85C51SND3B
Table 232. PSICON Register
PSICON (1.ADh) – PSI Control Register
Reset Value = 0000 0000b
Table 233. PSISTA Register
PSISTA (1.AEh) – PSI Status Register
PSEMPTY
Number
Number
PSEN
4-2
1-0
Bit
Bit
7
7
6
5
7
7
6
5
4
Mnemonic Description
Mnemonic Description
PSEMPTY
PSWS2:0
PSRUNE
PSBSYE
PSBSYE
PSRUN
PSBSY
PSRDY
PSBSY
PSEN
Bit
Bit
6
6
-
Interface Enable Bit
Set to enable the PSI controller.
Clear to disable the PSI controller.
Busy Interrupt Enable Bit
Set to enable the busy interrupt.
Clear to disable the busy interrupt.
Overrun/Underrun Interrupt Enable Bit
Set to enable the overrun interrupt.
Clear to disable the overrun interrupt.
Write Sampling Bits
Data write sampling wait states after WR signal assertion from 1 clock up to 7
clock periods
Reserved
The value read from these bits is always 0. Do not set these bits.
FIFO Empty Flag
Set by hardware when the FIFO is empty.
Cleared by hardware when at least one data byte is present in the FIFO.
Busy Flag
Set by hardware when the FIFO becomes not empty (host has sent data with
SA0 = H).
Can be set or cleared by software.
Overrun/Underrun Flag
Overrun
Set by hardware when the host sends a data and the FIFO is full.
Clear by software to acknowledge the overrun condition.
Underrun
Set by hardware when the host reads a data and the FIFO is empty.
Clear by software to acknowledge the underrun condition.
Ready Flag
Set by hardware when a data is ready to be sent to the host.
Cleared by hardware at the end of a host read cycle.
PSRUNE
PSOVR
5
5
PSWS2
PSRDY
4
4
PSWS1
3
3
-
PSWS0
2
2
-
1
1
-
-
7632D–MP3–01/07
0
0
-
-