at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 211

• Manufacturer Part Number: at85c51snd3
• Description: At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

Overrun - Underrun Conditions
Interrupts
7632D–MP3–01/07
Host can then read or write by burst an amount of data defined by the protocol (see
Section “Data Flow Controller”, page 78).
In order to avoid any underrun or overrun condition during burst transfer, host must be
slower than the DFC destination peripheral (host write) or the DFC source peripheral
(host read).
An overrun condition occurs when the hosts writes data quicker than the slave can con-
sume it.
An underrun condition occurs when the host read data quicker than the slave can
deliver it.
As soon as one of these two conditions is triggered, the PSRUN flag in PSISTA is set.
An interrupt can be generated when PSRUN bit is set by enabling PSRUNE bit in PSI-
CON while global PSI interrupt is enabled in IEN1 (see Figure 104).
Notes:
As shown in Figure 104, the PSI implements two interrupt sources reported in PSBSY
and PSRUN flags in PSISTA. These flags are detailed in the previous sections.
These sources are enabled separately using PSBSYE, and PSRUNE enable bits
respectively in PSICON.
The interrupt request is generated each time an enabled flag is set, and the global PSI
interrupt enable bit is set (EPSI in IEN1 register).
Figure 104. PSI Controller Interrupt System
PSISTA.6
PSRUN
PSISTA.5
PSBSY
1. Overrun and underrun conditions may appear in both transfer modes (CPU or DFC).
2. In overrun condition, the data written by the host is discarded.
3. In underrun condition, the data read by the host is the same as the previous one.
PSRUNE
PSBSYE
PSICON.6
PSICON.5
IEN1.2
EPSI
PSI
Interrupt
Request
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