at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 107

• Manufacturer Part Number: at85c51snd3
• Description: At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

Control Read
OUT Endpoint
Management
Overview
“Manual” Mode
7632D–MP3–01/07
USB line
RXSTPI
RXOUTI
TXINI
Wr Enable
HOST
Wr Enable
CPU
SETUP
SETUP
HW
The next figure shows a control read transaction. The USB controller has to manage the
simultaneous write requests from the CPU and the USB host:
A NAK handshake is always generated at the first status stage command.
When the controller detect the status stage, all the data written by the CPU are erased,
and clearing TXINI has no effects.
The firmware checks if the transmission is complete or if the reception is complete.
The OUT retry is always ack’ed. This reception:
- set the RXOUTI flag (received OUT data)
- set the TXINI flag (data sent, ready to accept new data)
software algorithm:
Once the OUT status stage has been received, the USB controller waits for a SETUP
request. The SETUP request have priority over any other request and has to be
ACK’ed. This means that any other flag should be cleared and the fifo reset when a
SETUP is received.
WARNING: the byte counter is reset when the OUT Zero Length Packet is received.
The firmware has to take care of this.
OUT packets are sent by the host. All the data can be read by the CPU, which acknowl-
edges or not the bank when it is empty.
The Endpoint must be configured first.
Each time the current bank is full, the RXOUTI and the FIFOCON bits are set. This trig-
gers an interrupt if the RXOUTE bit is set. The firmware can acknowledge the USB
interrupt by clearing the RXOUTI bit. The Firmware read the data and clear the FIFO-
CON bit in order to free the current bank. If the OUT Endpoint is composed of multiple
SW
set transmit ready
wait (transmit complete OR Receive complete)
if receive complete, clear flag and return
if transmit complete, continue
SW
IN
HW
DATA
SW
IN
OUT
NAK
STATUS
OUT
HW
SW
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