peb2035 ETC-unknow, peb2035 Datasheet - Page 78

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

CPA4 … CPA0 … Channel Address For Parity Check
Channel Loop Back (WRITE)
Value after RESET: 00
LOOP
AIA … Alarm Interrupt Acknowledge
SFM … Single Frame Mode
DLOP … Disable Channel Loop Back
CLA4 … CLA0 … Channel Address For Loop Back
Transmit Service Word Pulseframe (WRITE)
Value after RESET: 40
XSW
Semiconductor Group
0 … Normal operation
1 … Disables the channel loop back selected by this register. This bit should be set at least one
CPA = 0 … 31 selects the channel.
(NOT READABLE)
A ‘1’ written to this bit location clears the alarm interrupt signal at port AINT if the alarm
interrupt mode is enabled via bit CCR.AINT and register MASK, XSP.MXMB, XSP.MRMB
or XC1.MCA. Resetting this bit is not necessary.
Setting this bit reduces the receive speech memory from two to one frame length. In this
case, clocks SCLK and RRCLK have to be phase locked to avoid slip conditions. However,
slip detection still works but without any influence on data transmission.
time-slot before changing the channel address.
CLA = 1 … 31 selects the channel.
CLA =
During looped back the contents of the assigned outgoing channel at ports XDOP, XDOM,
XOID is equal to the idle channel code programmed at register IDLE.
7
7
XSIS
AIA
0 disables channel loop back.
H
H
SFM
1
DLOP
XRA
CLA4
XY0
78
XY1
XY2
XY3
CLA0
XY4
0
0
PEB 2035
(03)
(04)