peb2035 ETC-unknow, peb2035 Datasheet - Page 76

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

FRS … Force Resynchronization
SIM … Alarm Simulation
Mode Register (WRITE)
Value after RESET: 00
MODE
MFCS … Multiframe Force Resynchronization
AFR … Automatic Force Resynchronization
ENSN … Enable S
Semiconductor Group
0 … Normal operation.
1 … Initiates internal error simulation of AIS, no signal, loss of synchronization, slip, parity,
0 … Normal operation. The S
1 … S
A transition from low to high will initiate a resynchronization procedure of the pulse frame
and the CRC-multiframe (if enabled via bit MODE.CRC) starting directly after the old
framing candidate.
framing errors, CRC errors, and code violations. The error counters FEC, CVC, CEC will be
incremented.
Only valid if CRC multiframe format is selected.
A transition from low to high will initiate the resynchronization procedure for CRC-multiframe
alignment without influencing doubleframe synchronous state. In case, ‘Automatic Force
Resynchronization’ (MODE.AFR) is enabled and multiframe alignment can not be regained
a new search of doubleframe (and CRC multiframe) is automatically initiated.
Only valid if CRC multiframe format is selected.
If this bit is set, a search of doubleframe alignment is automatically initiated if two multiframe
pattern with a distance of n
doubleframe alignment has been regained or command MODE.MFCS has been issued.
Only applicable if MODE.CRC is set to one.
to bits RSW.RY0 … 4.
received information will be written to stack RSN. Transmitting contents of XSN will be
disabled if one of time-slot 0 transparent modes is enabled (XSP.TT0, XSP.TT0S,
EMOD.TT0X).
a
-bit stack mode. The S
7
MFCS
n
-Bit Stack
H
AFR
a
a
ENSN PMOD
-bit information will be taken from bits XSW.XY0 … 4 and written
-bit information will be taken from the stack XSN. In addition, the
2 ms have not been found within a time interval of 8 ms after
76
CRC
OPT
IMOD
XAIS
0
PEB 2035
(01)