peb2035 ETC-unknow, peb2035 Datasheet - Page 15

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

1.3
P-LCC
Pin No.
34
35
36
Semiconductor Group
Pin Definitions and Functions (cont’d)
P-DIP
Pin No.
30
31
32
Symbol
XDI
RESQ
ACKNLQ /
XSIG
Input (I)
Output (O)
I
I
I
Function
Transmit Data In
Transmit data received from the system internal
highway with 4096 kbit/s or 2048 kbit/s (bit
MODE.IMOD). Latching of data is done with
negative transitions of SCLK. The delay between
the beginning of time-slot 0 and the initial edge of
SCLK (after SYPQ goes active) is determined by
the values of transmit time-slot offset
XC1.XTO5 … 0 and transmit clock-slot offset
XC0 . XCO2 … 0. Additionally, for PCM 24 the
channel/time-slot correspondence between route
and system side is selected via bit MODE.CTM.
Reset (active low)
A low signal will initialize all internal flip flops. The
ACFA is switched to PCM 30 mode. All output
stages are tristated while RESQ is active.
DMA Acknowledge (active low)
If access to internal signaling stacks is enabled via
bit XCO.ISIG this input acts as an 'access enable'
to the internal stacks RSIG and XSIG in
conjunction with a read/write command without the
need of generating the chip enable signal CEQ. In
this case it should be connected to the
acknowledge output of the DMA controller to
enable IO-to-memory transfers.
PCM 30
No function if XCO.ISIG is set to '0'. In that case
this input has to be fixed either to V
PCM 24: Transmit Signaling Data
If XCO.ISIG is set to '0' the external signaling
mode is enabled. This port acts as input for the
signaling data requested by the marker XSIGM.
Latching of data is done with negative transitions
of SCLK. If not used port XSIG should be tied to
port XDI.
15
DD
PEB 2035
or to V
SS
.