peb2035 ETC-unknow, peb2035 Datasheet - Page 62

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

In the PCM 24 mode an additional possibility exists for using the FS/DL bits for signaling, e.g. for
CCS (see figure 14). For synchronizing this controller to the multiframe structure
– the time-slot internal flags
– the signals RMFB and XMFB, and
– the signals AFR and AFT (4-kHz DL clock)
may be used.
Figure 15
Connection to a Controller in FS/DL-Bit Application
c. Support for Direct Memory Access
Applications: CCS, CAS-CC, CAS-BR
After a DMA request, reading from and writing to the assigned stack must be done twice in the case
of PCM 30 mode and three times when PCM 24 mode is enabled.
Further handling of the signaling information is done automatically by the ACFA. In addition to the
signals for transfer control (RREQ, XREQ, ACKNLQ), the signals RMFB and XMFB may be used for
synchronization.
Acknowledging and clearing pending requests is done in one of the following ways:
XREQ bit EMOD.EDMA = ‘0’: at the end of the first write access to stack XSIG (rising edge of
Semiconductor Group
WRQ).
bit EMOD.EDMA = ‘1’: with the beginning of the second (PCM 30) or third (PCM 24) write
access to stack XSIG.XREQ is reset with the falling edge of ACKNLQ or CEQ and remains
reset if a write cycle to stack XSIG follows. Otherwise, it becomes active again until the
second or third access to stack XSIG is provided.
This stack is addressed by
1. address ‘A’ and write command (memory-to-memory DMA transfer)
2. signal: ACKNLQ and write command (memory-to-I/O DMA transfer)
PEB 2035
ACFA
PCM 24 only
XSIG
RDO
XDI
RMFB
XMFB
AFR
AFT
62
Controller
FS/DL
ITS03585
PEB 2045
MTSC
SYPQ
PEB 2035