peb2035 ETC-unknow, peb2035 Datasheet - Page 133

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

Additions to PCM 24 mode
Semiconductor Group
Doubleframe Format with Support of Sn-Bit Stacks
As extension to standard doubleframe format the internal 5-byte Sn-bit stacks RSN and XSN can
be used (refer to EMOD.DFSN).
Corrections: generation of signal XREQ and read-back option of XSP.XS13, XSP.XS15.
CRC Alarm Interrupt
As an extension of the alarm interrupt capabilities, the occurrence of a CRC error can be defined
as interrupt source (XC1.MCA) for triggering interrupt port AINT.
CRC6 Inversion
If enabled via bit GCR.CRCI, all CRC bits of one outgoing extended multiframe are inverted in
case a CRC error is flagged for the previous received multiframe.
Idle Code Insertion
In transmit direction, the contents of selectable channel can be overwritten by the pattern defined
via register IDLE. The selection of ‘idle channels’ is done by programming the three-byte register
bank ICB1 ... ICB3 (enabled via CPY.SW and CPY.BSEL).
Selectable Conditions for Loss of Synchronization
Selection is provided via bit RC1.SLC between ‘2 errors out of 4’ or ‘2 errors out of 5’ FT/FS bits.
Selectable Sync/Resync Procedure for F12 and F72 Format
FT and FS bit conditions, i.e. pulse frame alignment and multiframe alignment can be handled
separately if programmed via bit EMOD.SSP.
Multiframe Begin Signal
Signals RMFB and XMFB indicate only the multiframe begin. Additional pulses (every 12 frames)
are disabled via bit ACR.MFBS.
4-kHz DL Clock
If programmed via bit ACR.DLC, ports RCHPY and XCHPY provide signals which mark the DL-
bit position within the data stream at RDO and XDI.
AIS Indication
The AIS indication algorithm is changed to detect AIS even in the presence of BER 10**-3 (bit
GCR.AISM).
Remote Alarm Indication
Algorithms are changed to detect remote alarm even in the presence of BER 10**-3 (bit
RC1.RRAM).
Transparent Mode
Setting bit GCR.TM switches the ACFA in transparent mode:
– In transmit direction bit 8 of the FS/DL time-slot from the system internal highway (XDI) is
inserted in the F-bit position of the outgoing frame.
– In receive direction the framing bit is also forwarded to RDO and inserted in the FS/DL time-
slot. Bit RDCF (bit 1 of FS/DL time-slot) indicates a DL bit.
133
PEB 2035