peb2035 ETC-unknow, peb2035 Datasheet - Page 39

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

Line Interfacing
General Aspects of Synchronization
Synchronization status is reported via bit RSR.LOS (Loss Of Synchronization). Framing errors
(pulse frame and multiframe) are counted by the Framing Error Counter FEC.
Asynchronous state is reached if
framing bits (terminal framing or multiframing) are incorrect. If auto-mode is enabled, counting of
framing errors is interrupted.
The resynchronization procedure can be controlled by either one of the following procedure:
Addition for F12 and F72 Format
FT and FS bit conditions, i.e. pulse frame alignment and multiframe alignment can be handled
separately if programmed via bit EMOD.SSP. Thus, a multiframe re-synchronization can be
automatically initiated after detecting 2 errors out of 4/5 consecutive multiframing bits without
influencing the state of the terminal framing.
In the synchronous state, the setting of CCR.FRS or CCR.EXLS resets the synchronizer and
initiates a new frame search. The synchronous state is reached if there is only one definite framing
candidate. In the case of repeated apparent simulated candidates, the synchronizer remains in the
asynchronous state.
In asynchronous state, the function of CCR.EXLS is the same as above. Setting bit CCR.FRS
induces the synchronizer to lock onto the next available framing candidate if there is one.
Otherwise, a new frame search is started. This is useful in case the framing pattern that defines the
pulseframe position is imitated periodically by a pattern in one of the speech/data channels. The F-
bit Error History (FSR.FEH5 … 0) may be used in the decision whether to initiate resynchronization.
The control bit CCR.EXLS should be used first because it starts the synchronizer to search for a
definite framing candidate.
To observe actions of the synchronizer, the Frame Search Restart Flag RSR.FSRF is implemented.
It toggles at the start of a new frame search if no candidate has been found at previous attempt.
Semiconductor Group
The updating of these bits depends on the resynchronization mode:
Dual rail data with B8ZS or AMI (ZCS) coding (selection via bit MODE.CODE). All code violations
which do not correspond to zero code substitution rules are registrated by the Code Violation
Counter (CVC) with 8- or 10-bit length (selected via bit EMOD.ECVE).
If AMI coding with zero code suppression (B7-stuffing) is selected, ‘clear channels’ without B7-
stuffing can be defined by programming registers CCB1 … CCB3.
Single rail unipolar data with no zero suppression algorithm (MODE.OPT = 1).
2 out of 4 (bit RC1.SLC reset), or
2 out of 5 (bit RC1.SLC set)
automatically (GCR.AUTO = 1). Additionally, it may be triggered by the user by setting/resetting
one of the bits CCR.FRS (Force Resynchronization) or CCR.EXLS (External Loss of Frame).
user controlled, exclusively, via above control bits in the non-auto-mode (GCR.AUTO = 0).
Auto mode: updating only during the synchronous state.
Non-auto-mode: updating during the synchronous state and
until one of the above control bits are set during the asynchronous state.
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PEB 2035