ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 96
ep1agx50d
Manufacturer Part Number
ep1agx50d
Description
Arria Gx Device Data Sheet
Manufacturer
Altera Corporation
Datasheet
1.EP1AGX50D.pdf
(296 pages)
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PLLs and Clock Networks
2–88
Arria GX Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
(5)
EP1AGX20
EP1AGX35
EP1AGX50
EP1AGX60(5)
EP1AGX90
Table 2–17. Arria GX Device PLL Availability
The global or regional clocks in a fast PLL's transceiver block can drive the fast PLL input. A pin or other PLL must
drive the global or regional source. The source cannot be driven by internally generated logic before driving the fast
PLL.
EP1AGX20C, EP1AGX35C/D, EP1AGX50C and EP1AGX60C/D devices only have two fast PLLs (PLLs 1 and 2), but
the connectivity from these two PLLs to the global and regional clock networks remains the same as shown in this
table.
PLLs 3, 4, 9, and 10 are not available in Arria GX devices.
4 or 8 PLLs are available depending on C or D device and the package option.
4or 8 PLLs are available depending on C, D, or E device option.
Device
Table
(4)
2–17:
v
v
v
v
v
1
v
v
v
v
v
2
The Quartus II software enables the PLLs and their features without
requiring any external devices.
each Arria GX device and their type.
3
(3)
4
(3)
Fast PLLs
Notes
v
v
v
7
(1),
v
v
v
8
(2)
Table 2–17
9
(3)
10
shows the PLLs available for
(3)
v
v
v
v
v
5
Enhanced PLLs
Altera Corporation
v
v
v
v
v
6
v
v
v
11
May 2008
v
v
v
12
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