ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 289

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
May 2008
Notes to
(1)
(2)
(3)
Table 4–120. DQS Phase-Shift Error Specifications for DLL-Delayed Clock
(t
Table 4–121. DQS Bus Clock Skew Adder Specifications
(t
Table 4–122. DQS Phase Offset Delay Per Stage (ps)
DQS_PSERR
DQS_CLOCK_SKEW_ADDER
The delay settings are linear.
The valid settings for phase offset are -32 to +31.
The typical value equals the average of the minimum and maximum values.
Speed Grade
Number of DQS Delay Buffer Stages
Table
-6
18 DQ per DQS
36 DQ per DQS
)
4 DQ per DQS
9 DQ per DQS
4–122:
Mode
)
1
2
3
4
Min
10
Positive Offset
Arria GX Device Handbook, Volume 1
Max
16
DC and Switching Characteristics
DQS Clock Skew Adder (ps)
–6 Speed Grade (ps)
Min
Negative Offset
Notes
8
40
70
75
95
105
140
(1), (2),
35
70
Max
12
(3)
4–135