ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 196

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

I/O Timing Model
4–42
Arria GX Device Handbook, Volume 1
Notes to
(1)
Clock skew adder
EP1AGX90
Table 4–46. Clock Network Specifications (Part 2 of 2)
This is in addition to intra-clock network skew, which is modeled in the Quartus II software.
Table
Name
(1)
4–46:
Inter-clock network, same side
Inter-clock network, entire chip
Default Capacitive Loading of Different I/O Standards
See
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
PCI
PCI-X
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential SSTL-18 Class II
1.5-V differential HSTL Class I
1.5-V differential HSTL Class II
1.8-V differential HSTL Class I
Table 4–47. Default Loading of Different I/O Standards for Arria GX
Devices (Part 1 of 2)
Table 4–47
Description
I/O Standard
for default capacitive loading of different I/O standards.
Min
Capacitive Load
Typ
10
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Altera Corporation
± 110
Max
± 55
May 2008
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Unit
ps
ps