ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 14

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Transceivers
Figure 2–4. Transmitter PLL
Notes to
(1)
(2)
2–6
Arria GX Device Handbook, Volume 1
Inter-Transceiver Lines
Global Clock
Dedicated
REFCLK0
Dedicated
REFCLK1
Inter-Transceiver Lines[2:0]
You only need to select the protocol and the available input reference clock frequency in the ALTGXB MegaWizard
Plug-In Manager. Based on your selections, the MegaWizard Plug-In Manager automatically selects the necessary
/M and /L dividers (clock multiplication factors).
The global clock line must be driven from an input pin only.
To
Figure
(2)
2–4:
/2
/2
Figure 2–4
The reference clock input to the transmitter PLL can be derived from:
■
■
■
1
Table 2–2
Input reference frequency range
Data rate support
Bandwidth
Table 2–2. Transmitter PLL Specifications
One of two available dedicated reference clock input pins (REFCLK0
or REFCLK1) of the associated transceiver block
PLD global clock network (must be driven directly from an input
clock pin and cannot be driven by user logic or enhanced PLL)
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
INCLK
Altera
pins (REFCLK0 or REFCLK1) to provide reference clock for the
transmitter PLL.
lists the adjustable parameters in the transmitter PLL.
shows the block diagram of the transmitter PLL.
Parameter
Frequency
®
Detector
Phase
recommends using the dedicated reference clock input
down
up
/M
(1)
Pump + Loop
Charge
Filter
600 Mbps to 3.125 Gbps
Controlled
Oscillator
50 MHz to 622.08 MHz
Voltage
Low, medium, or high
Transmitter PLL
Specifications
/L
Altera Corporation
(1)
May 2008
Serial Clock
High Speed