ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 40

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Transceivers
Figure 2–22. Input Reference Clock Sources
2–32
Arria GX Device Handbook, Volume 1
Inter-Transceiver Lines [2]
Inter-Transceiver Lines [1]
Inter-Transceiver Lines [0]
f
Dedicated
REFCLK0
Dedicated
REFCLK1
Inter-Transceiver Lines [2:0]
Figure 2–22
and receiver PLL.
For detailed transceiver clocking in all supported functional modes, refer
to the
Arria GX Device Handbook.
PLD Clock Utilization by Transceiver Blocks
Arria GX devices have up to 16 global clock (GCLK) lines and 16 regional
clock (RCLK) lines that are used to route the transceiver clocks. The
following transceiver clocks utilize the available global and regional clock
resources:
■
■
■
■
Global Clock (1)
pll_inclk (if driven from an FPGA input pin)
rx_cruclk (if driven from an FPGA input pin)
tx_clkout/coreclkout (CMU low-speed parallel clock
forwarded to the PLD)
Recovered clock from each channel (rx_clkout) in non-rate
matcher mode
Arria GX Transceiver Architecture
Global Clock (1)
shows the input reference clock sources for the transmitter
/2
/2
chapter in volume 2 of the
Transceiver Block 0
Transmitter
Receiver
PLL
PLLs
Transceiver Block 1
Four
Transceiver Block 2
Altera Corporation
May 2008