ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 93

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Figure 2–58. Global Clock Control Blocks
Notes to
(1)
(2)
Figure 2–59. Regional Clock Control Blocks
Notes to
(1)
(2)
Altera Corporation
May 2008
These clock select signals can be dynamically controlled through internal logic when the device is operating in user
mode.
These clock select signals can only be set through a configuration file (SRAM Object File [.sof] or Programmer Object
File [.pof]) and cannot be dynamically controlled during user mode operation.
These clock select signals can only be set through a configuration file (SOF or POF) and cannot be dynamically
controlled during user mode operation.
Only the CLKn pins on the top and bottom of the device feed to regional clock select.
Figure
Figure
2–58:
2–59:
CLKSELECT[1..0]
(1)
This multiplexer supports
User-Controllable
Dynamic Switching
PLL Counter
PLL Counter
Outputs
Outputs
2
2
2
CLKp
CLKp
Pins
Pin
Enable/
Disable
RCLK
2
CLKn
Pin
Enable/
Disable
GCLK
CLKn
Pin
(2)
Internal
Logic
Static Clock Select (1)
Internal
Logic
Internal
Logic
Internal
Static Clock Select
Logic
Arria GX Device Handbook, Volume 1
(2)
Arria GX Architecture
2–85