ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 94

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

PLLs and Clock Networks
Figure 2–60. External PLL Output Clock Control Blocks
Notes to
(1)
(2)
2–86
Arria GX Device Handbook, Volume 1
These clock select signals can only be set through a configuration file (SOF or POF) and cannot be dynamically
controlled during user mode operation.
The clock control block feeds to a multiplexer within the PLL_OUT pin’s IOE. The PLL_OUT pin is a dual-purpose
pin. Therefore, this multiplexer selects either an internal signal or the output of the clock control block.
Figure
2–60:
For the global clock control block, clock source selection can be controlled
either statically or dynamically. You has the option of statically selecting
the clock source by using the Quartus II software to set specific
configuration bits in the configuration file (
the selection dynamically by using internal logic to drive the multiplexer
select inputs. When selecting statically, the clock source can be set to any
of the inputs to the select multiplexer. When selecting the clock source
dynamically, you can either select between two PLL outputs (such as the
C0 or C1 outputs from one PLL), between two PLLs (such as the C0/C1
clock output of one PLL or the C0/C1 c1ock output of the other PLL),
between two clock pins (such as CLK0 or CLK1), or between a
combination of clock pins or PLL outputs.
For the regional and PLL_OUT clock control block, clock source selection
can only be controlled statically using configuration bits. Any of the
inputs to the clock select multiplexer can be set as the clock source.
IOE
Internal
Logic
(2)
Outputs (c[5..0])
PLL Counter
PLL_OUT
Enable/
Disable
Pin
6
Internal
Static Clock
Select (1)
Logic
Static Clock Select
(1)
SOF or POF
) or you can control
Altera Corporation
May 2008