ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 267

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Maximum Input
and Output Clock
Toggle Rate
Altera Corporation
May 2008
Delay from
output register
to output pin
Output enable
pin delay
Input delay
from pin to
internal cells
Input delay
from pin to
input register
Delay from
output register
to output pin
Output enable
pin delay
Table 4–100. Arria GX IOE Programmable Delay on Row Pins (Part 2 of 2)
Table 4–101. Arria GX IOE Programmable Delay on Column Pins
Parameter
Parameter
Pad to I/O
Pad to I/O
dataout to
I/O output
register to
Affected
register
I/O output
register to
txz/tzx
Paths
input
Affected
core
pad
txz/tzx
Paths
pad
Table 4–101
Maximum clock toggle rate is defined as the maximum frequency
achievable for a clock type signal at an I/O pin. The I/O pin can be a
regular I/O pin or a dedicated clock I/O pin.
The maximum clock toggle rate is different from the maximum data bit
rate. If the maximum clock toggle rate on a regular I/O pin is 300 MHz,
the maximum data bit rate for dual data rate (DDR) could be potentially
as high as 600 Mbps on the same I/O pin.
Available
Settings
Available
Settings
64
8
2
2
2
2
describes IOE programmable delays.
Offset
Min
Offset
0
0
0
0
Min
Industrial
0
0
Industrial
Offset
1.781
2.053
0.332
Max
0.32
Offset
0.332
Max
0.32
Fast Model
Fast Model
Offset
Min
Offset
Commercial
Min
0
0
0
0
Commercial
0
0
Arria GX Device Handbook, Volume 1
DC and Switching Characteristics
Offset
1.781
2.053
0.332
Max
0.32
Offset
0.332
Max
0.32
Offset
-6 Speed Grade
Offset
-6 Speed Grade
Min
Min
0
0
0
0
0
0
Offset
4.132
4.697
0.717
0.693
Offset
0.717
0.693
Max
Max
4–113
Units
Units
ns
ns
ns
ns
ns
ns