ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 65
ep1agx50d
Manufacturer Part Number
ep1agx50d
Description
Arria Gx Device Data Sheet
Manufacturer
Altera Corporation
Datasheet
1.EP1AGX50D.pdf
(296 pages)
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Figure 2–40. Shared Arithmetic Chain, Carry Chain and Register Chain Interconnects
Altera Corporation
May 2008
Routing to Adjacent ALM
Carry Chain & Shared
C4 interconnects span four LABs, M512, or M4K blocks up or down from
a source LAB. Every LAB has its own set of C4 interconnects to drive
either up or down.
from a LAB in a column. C4 interconnects can drive and be driven by all
types of architecture blocks, including DSP blocks, TriMatrix memory
blocks, and column and row IOEs. For LAB interconnection, a primary
LAB or its LAB neighbor can drive a given C4 interconnect. C4
interconnects can drive each other to extend their range as well as drive
row interconnects for column-to-column connections.
Arithmetic Chain
Interconnect
Local
Figure 2–41
Local Interconnect
Routing Among ALMs
in the LAB
ALM 1
ALM 2
ALM 3
ALM 4
ALM 5
ALM 6
ALM 7
ALM 8
shows the C4 interconnect connections
Register Chain
Routing to Adjacent
ALM's Register Input
Arria GX Device Handbook, Volume 1
Arria GX Architecture
2–57
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