ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 130

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

I/O Structure
2–122
Arria GX Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
V
Table 2–27. Arria GX MultiVolt I/O Support
CCIO
1.2
1.5
1.8
2.5
3.3
To drive inputs higher than V
the Allow LVTTL and LVCMOS input levels to overdrive input buffer option in the Quartus II
software.
The pin current may be slightly higher than the default value. You must verify that the driving
device’s V
maximum and V
Although V
device powered at a different level can still interface with the Arria GX device if it has inputs that
tolerate the V
Arria GX devices support 1.2-V HSTL. They do not support 1.2-V LVTTL and 1.2-V LVCMOS.
(V)
Table
1.2
(4)
(4)
(4)
(4)
(4)
Table 2–27
The TDO and nCEO pins are powered by V
TDO is in I/O bank 4 and nCEO is in I/O Bank 7. Ideally, the V
for the I/O buffers of any two connected pins are at the same voltage
level. This may not always be possible depending on the V
TDO and nCEO pins on master devices and the configuration voltage level
chosen by V
position in the chain. Master indicates that it is driving out TDO or nCEO
to a slave device. For multi-device passive configuration schemes, the
nCEO pin of the master device will be driving the nCE pin of the slave
device. The VCCSEL pin on the slave device selects which input buffer is
used for nCE. When V
powered by V
input buffer powered by V
nCEO bank in a master device match the V
buffer of the slave device it is connected to, but that may not be possible
depending on the application.
O L
2–27:
CCIO
CCIO
maximum and V
v
1.5
specifies the voltage necessary for the Arria GX device to drive out, a receiving
v
v
I H
value.
(2)
minimum voltage specifications.
Input Signal (V)
summarizes Arria GX MultiVolt I/O support.
CCSEL
v
1.8
v
v
CCIO
(2)
CCIO
O H
on slave devices. Master and slave devices can be in any
. When V
minimum voltages do not violate the applicable Arria GX V
but less than 4.0 V, disable the PCI clamping diode and select
v
v
v
2.5
v
v
CCSEL
(2)
(2)
(2)
CCPD
CCSEL
is logic high, it selects the 1.8-V/1.5-V buffer
v
v
v
3.3
Note (1)
v
v
(2)
(2)
(2)
. The ideal case is to have the V
is logic low it selects the 3.3-V/2.5-V
v
v
v
v
v
1.2
(4)
(3)
(3)
(3)
(3)
CCIO
CCSEL
v
v
v
1.5
v
(3)
(3)
(3)
of the bank that they reside.
Output Signal (V)
settings for the nCE input
v
v
1.8
v
(3)
(3)
Altera Corporation
v
2.5
v
CCIO
(3)
CC
CCIO
level of
May 2008
supplies
3.3 5.0
v
of the
v
I L