ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 88

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

PLLs and Clock Networks
PLLs and Clock
Networks
2–80
Arria GX Device Handbook, Volume 1
Arria GX devices provide a hierarchical clock structure and multiple
phase-locked loops (PLLs) with advanced features. The large number of
clocking resources in combination with the clock synthesis precision
provided by enhanced and fast PLLs provides a complete clock
management solution.
Global and Hierarchical Clocking
Arria GX devices provide 16 dedicated global clock networks and
32 regional clock networks (eight per device quadrant). These clocks are
organized into a hierarchical clock structure that allows for up to 24 clocks
per device region with low skew and delay. This hierarchical clocking
scheme provides up to 48 unique clock domains in Arria GX devices.
There are 12 dedicated clock pins (CLK[15..12] and CLK[7..0]) to
drive either the global or regional clock networks. Four clock pins drive
each side of the device except the right side, as shown in
2–55. Internal logic and enhanced and fast PLL outputs can also drive the
global and regional clock networks. Each global and regional clock has a
clock control block, which controls the selection of the clock source and
dynamically enables or disables the clock to reduce power consumption.
Table 2–16
Global Clock Network
These clocks drive throughout the entire device, feeding all device
quadrants. Global clock networks can be used as clock sources for all
resources in the device IOEs, ALMs, DSP blocks, and all memory blocks.
These resources can also be used for control signals, such as clock enables
and synchronous or asynchronous clears fed from the external pin. The
global clock networks can also be driven by internal logic for internally
Number per device
Number available per
quadrant
Sources
Dynamic clock source
selection
Dynamic enable/disable
Table 2–16. Global and Regional Clock Features
Feature
shows the global and regional clock features.
Clock pins, PLL outputs,
inter-transceiver clocks
Global Clocks
core routings,
v
v
16
16
Clock pins, PLL outputs,
inter-transceiver clocks
Regional Clocks
Altera Corporation
core routings,
Figures 2–54
v
32
8
May 2008
and