ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 89

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Figure 2–54. Global Clocking
Altera Corporation
May 2008
CLK[3..0]
generated global clocks and asynchronous clears, clock enables, or other
control signals with large fanout.
pins driving global clock networks.
Regional Clock Network
There are eight regional clock networks (RCLK[7..0]) in each quadrant
of the Arria GX device that are driven by the dedicated
CLK[15..12]and CLK[7..0] input pins, by PLL outputs, or by internal
logic. The regional clock networks provide the lowest clock delay and
skew for logic contained in a single quadrant. The CLK pins
symmetrically drive the RCLK networks in a particular quadrant, as
shown in
Figure
Global Clock [15..0]
2–55.
CLK[7..4]
CLK[15..12]
Figure 2–54
Global Clock [15..0]
Arria GX Device Handbook, Volume 1
shows the 12 dedicated CLK
Arria GX Architecture
2–81