ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 49

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
May 2008
One ALM contains two programmable registers. Each register has data,
clock, clock enable, synchronous and asynchronous clear, asynchronous
load data, and synchronous and asynchronous load/preset inputs.
Global signals, general-purpose I/O pins, or any internal logic can drive
the register's clock and clear control signals. Either general-purpose I/O
pins or internal logic can drive the clock enable, preset, asynchronous
load, and asynchronous load data. The asynchronous load data input
comes from the datae or dataf input of the ALM, which are the same
inputs that can be used for register packing. For combinational functions,
the register is bypassed and the output of the LUT drives directly to the
outputs of the ALM.
Each ALM has two sets of outputs that drive the local, row, and column
routing resources. The LUT, adder, or register output can drive these
output drivers independently (see
drivers, two ALM outputs can drive column, row, or direct link routing
connections. One of these ALM outputs can also drive local interconnect
resources. This allows the LUT or adder to drive one output while the
register drives another output. This feature, called register packing,
improves device utilization because the device can use the register and
combinational logic for unrelated functions. Another special packing
mode allows the register output to feed back into the LUT of the same
ALM so that the register is packed with its own fan-out LUT. This feature
provides another mechanism for improved fitting. The ALM can also
drive out registered and unregistered versions of the LUT or adder
output.
ALM Operating Modes
The Arria GX ALM can operate in one of the following modes:
■
■
■
■
Each mode uses ALM resources differently. Each mode has 11 available
inputs to the ALM (see
local interconnect; carry-in from the previous ALM or LAB; the shared
arithmetic chain connection from the previous ALM or LAB; and the
register chain connection ⎯ are directed to different destinations to
implement the desired logic function. LAB-wide signals provide clock,
asynchronous clear, asynchronous preset/load, synchronous clear,
synchronous load, and clock enable control for the register. These
Normal mode
Extended LUT mode
Arithmetic mode
Shared arithmetic mode
Figure
2–28) ⎯ the eight data inputs from the LAB
Figure
Arria GX Device Handbook, Volume 1
2–29). For each set of output
Arria GX Architecture
2–41