ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 91

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Figure 2–56. Dual-Regional Clocks
Altera Corporation
May 2008
PLLs
CLK[3..0]
Clock Pins or PLL Clock Outputs
Can Drive Dual-Regional Network
CLK[7..4]
Combined Resources
Within each quadrant, there are 24 distinct dedicated clocking resources
consisting of 16 global clock lines and eight regional clock lines.
Multiplexers are used with these clocks to form buses to drive LAB row
clocks, column IOE clocks, or row IOE clocks. Another multiplexer is
used at the LAB level to select three of the six row clocks to feed the ALM
registers in the LAB (see
CLK[15..12]
Figure
Clock Pins or PLL Clock
Outputs Can Drive
Dual-Regional Network
PLLs
CLK[3..0]
2–57).
Arria GX Device Handbook, Volume 1
CLK[7..4]
Arria GX Architecture
CLK[15..12]
2–83