AN1849 Motorola / Freescale Semiconductor, AN1849 Datasheet - Page 6

• Manufacturer Part Number: AN1849
• Description: MPC107 Design Guide
• Manufacturer: Motorola / Freescale Semiconductor

The DLL in the MPC107 is similar to a PLL except that it divides the clock period into discrete intervals,
in this case into 128 intervals. The DLL drives the SDRAM_SYNC_OUT signal and measures the number
of intervals until the clock is detected on the SDRAM_SYNC_IN pin. As trace length is added to the
feedback path (SDRAM_SYNC_OUT to SDRAM_SYNC_IN), the DLL numerically adjusts the delay to
the next clock edge so that the SDRAM_CLK signals starts sooner, relative to the internal bus clock
(referred to as “sys_logic_clk”).
Why sooner? The assumption is that the clock and data traces to the SDRAM are all of equal length, but that
the control signals are more heavily loaded (often true), or that additional output hold time is needed for
SDRAM. The usual way of compensating for such issues is to add trace delay to the SDRAM clocks, but
this can take a lot of board space with four or more clocks. By adding the trace delay to the feedback path
alone, less board space is required, design is easier, and routing the board is easier. An example of the effect
of lengthening SDRAM feedback path is shown in Figure 4.
To understand the MPC107 DLL clock generator, it is essential to realize that the DLL has absolutely no
effect whatsoever on the AC timing of any SDRAM signal. All MPC107 signals are synchronous to the
internal core bus clock, sys_logic_clk, regardless of what length feedback path is used. The only signals
affected by the DLL are SDRAM_CLK(0:3), CPU_CLK(0:2) and SDRAM_SYNC_OUT.
1.4.4 Clocking and SDRAM Memory Systems
Section 1.5.2 covers the connections of the memory system; these are relatively straightforward but clocks
need special treatment - they are the heart of an SDRAM memory system. Assuming good layout techniques
are used and the traces for the SDRAM controls, data and clocks are kept relatively equalized (traces routed
to the same lengths, to within
SDRAM components.
To determine the timing adjustments, it is necessary to determine what effect PCB trace length and SDRAM
component loads have on the propagation delay. This application note is not going to rehash an entire book’s
worth of electromagnetic wave equation derivations; instead, the appendix has several good references for
a designer to refer to in checking that the assumptions used here are a good match for the design. If not,
slight modifications these equations will be needed.
6
SDRAM_SYNC_OUT
SDRAM_SYNC_OUT
SDRAM_SYNC_IN
SDRAM_SYNC_IN
MPC107
MPC107
SDRAM_CLK0
SDRAM_CLK0
≅ 0 cm
≅ 0 ps
Figure 4. SDRAM Feedback Path Overview
±
10%), then the DLL of the MPC107 can be used to set the timing for the
≅ 16.5 cm
≅ 1000 ps
MPC107 Design Guide
to SDRAM
to SDRAM
SDRAM SYNC_OUT
SDRAM SYNC_OUT
SDRAM_SYNC_IN
SDRAM_SYNC_IN
SDRAM_CLK0
SDRAM_CLK0
sys_logic_clk
sys_logic_clk