AN1849 Motorola / Freescale Semiconductor, AN1849 Datasheet - Page 27

• Manufacturer Part Number: AN1849
• Description: MPC107 Design Guide
• Manufacturer: Motorola / Freescale Semiconductor

END BEHAVIOR;
1.8.2 Multiprocessing Interrupts
While the MPC107 supports two processors on the processor bus, the EPIC interrupt controller supports
only one CPU (and one interrupt output, INT). This architecture is acceptable for non-SMP use as long as
one CPU can be dedicated to processing all interrupts. It is basically not possible to achieve SMP
(symmetric multiprocessing) if the EPIC unit is involved, since the second processor is essentially relegated
to co-processor status. To get around these limitations, the designer can:
The first two methods are straightforward engineering, and will not be covered further. The third is
somewhat different: it uses the capability of the I2O message unit to allow the first processor to interrupt the
second processor. This is shown in Figure 20, which also shows the flow of an interrupt from PCI to a second
processor.
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•
•
•
Use an external OpenPIC to route MPC107 or PCI interrupts to either processor.
Use an external interrupt controller to collect non-MPC107 interrupts for the second processor.
Use the INTA to interrupt the second MPC107.
Connect the MPC107 INT output to both CPUs.
END PROCESS output;
ELSIF (q = '1000') THEN
ELSIF (q = '1001') THEN
ELSIF (q = '1010') THEN
ELSIF (q = '1011') THEN
ELSIF (q = '1100') THEN
ELSIF (q = '1101') THEN
ELSIF (q = '1110') THEN
ELSE
END IF;
s_int <= int_B(7);
s_int <= int_B(8);
s_int <= int_B(9);
s_int <= int_B(10);
s_int <= int_B(11);
s_int <= int_B(12);
s_int <= int_B(13);
s_int <= int_B(14);
s_int <= int_B(15);
MPC107 Design Guide
Interrupt Controller
27