AN1849 Motorola / Freescale Semiconductor, AN1849 Datasheet - Page 30

• Manufacturer Part Number: AN1849
• Description: MPC107 Design Guide
• Manufacturer: Motorola / Freescale Semiconductor

Assuming that the UART is a typical PC16550-compatible device, it has 8 sequentially-addressable
registers. When this device is attached to the most-significant bits of the memory data bus, MDH(0:7), the
8-bit registers will appear every eight locations in memory, as shown in Table 11.
The important thing to notice is that the MPC107 still performs 64-bit reads and writes to those locations.
When the MPC107 reads from the UART, it will latch in 8 bits of data on MDH(0:7) and 56 bits of random
data from MDH(8:31)+MDL(0:31). As long as byte read instructions are used, anything on the unused byte
lanes will be ignored. For write instructions, the MPC107 expects that the I/O device will not monitor
unused byte lanes; for this reason, I/O devices cannot share chip selects by using different byte lanes.
In the above example, if the UART had been connected to the least-significant bits of the memory data bus,
the addresses would have required an offset to select the proper byte lane. For MDL(24:31), the offset is 7,
so the sequential UART addresses would be 0x7C00_0007, 0x7C00_000F, 0x7C00_0017, etc. For
high-speed or highly-loaded systems, this technique can be used to minimize loading effects which would
occur if every I/O device (as well as memory) is attached to DH(0:7).
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ADDRESS
7C00_0000
7C00_0008
7C00_0010
7C00_0018
MDH(0:7)
REG #3
REG #1
REG #2
REG #0
UART
UART
UART
UART
UART
...
0
MDH(8:15) MDH(16:23)
NOTE: Assuming 64-bit RCS2 ROM width
RBR / THR
1
IIR / FCR
Register
UART
MCR
Table 11. Example UART Address Mapping
MSR
SCR
LCR
LSR
IER
Figure 22. Reduced Bus Width for I/O
2
MPC107 Design Guide
Address
MDH(24:31)
UART
0
1
2
3
4
5
6
7
3
unused
MDL(0:7)
MPC107 I/O Address
4
0x7C00_0000
0x7C00_0008
0x7C00_0010
0x7C00_0018
0x7C00_0020
0x7C00_0028
0x7C00_0030
0x7C00_0038
MDL(8:15)
5
MDL(16:23) MDL(24:31)
6
7
OFFSET
BYTE LANE